RegViz: Visualize INT

Espressif Systems /ESP32-P4 /RMT /INT_ST

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INT_ST

Description

Masked interrupt status

Fields

CH0_TX_END_INT_ST	The masked interrupt status bit for CH0_TX_END_INT.
CH1_TX_END_INT_ST	The masked interrupt status bit for CH1_TX_END_INT.
CH2_TX_END_INT_ST	The masked interrupt status bit for CH2_TX_END_INT.
CH3_TX_END_INT_ST	The masked interrupt status bit for CH3_TX_END_INT.
TX_CH0_ERR_INT_ST	The masked interrupt status bit for CH0_ERR_INT.
TX_CH1_ERR_INT_ST	The masked interrupt status bit for CH1_ERR_INT.
TX_CH2_ERR_INT_ST	The masked interrupt status bit for CH2_ERR_INT.
TX_CH3_ERR_INT_ST	The masked interrupt status bit for CH3_ERR_INT.
CH0_TX_THR_EVENT_INT_ST	The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
CH1_TX_THR_EVENT_INT_ST	The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
CH2_TX_THR_EVENT_INT_ST	The masked interrupt status bit for CH2_TX_THR_EVENT_INT.
CH3_TX_THR_EVENT_INT_ST	The masked interrupt status bit for CH3_TX_THR_EVENT_INT.
CH0_TX_LOOP_INT_ST	The masked interrupt status bit for CH0_TX_LOOP_INT.
CH1_TX_LOOP_INT_ST	The masked interrupt status bit for CH1_TX_LOOP_INT.
CH2_TX_LOOP_INT_ST	The masked interrupt status bit for CH2_TX_LOOP_INT.
CH3_TX_LOOP_INT_ST	The masked interrupt status bit for CH3_TX_LOOP_INT.
CH4_RX_END_INT_ST	The masked interrupt status bit for CH4_RX_END_INT.
CH5_RX_END_INT_ST	The masked interrupt status bit for CH5_RX_END_INT.
CH6_RX_END_INT_ST	The masked interrupt status bit for CH6_RX_END_INT.
CH7_RX_END_INT_ST	The masked interrupt status bit for CH7_RX_END_INT.
RX_CH4_ERR_INT_ST	The masked interrupt status bit for CH4_ERR_INT.
RX_CH5_ERR_INT_ST	The masked interrupt status bit for CH5_ERR_INT.
RX_CH6_ERR_INT_ST	The masked interrupt status bit for CH6_ERR_INT.
RX_CH7_ERR_INT_ST	The masked interrupt status bit for CH7_ERR_INT.
CH4_RX_THR_EVENT_INT_ST	The masked interrupt status bit for CH4_RX_THR_EVENT_INT.
CH5_RX_THR_EVENT_INT_ST	The masked interrupt status bit for CH5_RX_THR_EVENT_INT.
CH6_RX_THR_EVENT_INT_ST	The masked interrupt status bit for CH6_RX_THR_EVENT_INT.
CH7_RX_THR_EVENT_INT_ST	The masked interrupt status bit for CH7_RX_THR_EVENT_INT.
TX_CH3_DMA_ACCESS_FAIL_INT_ST	The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT.
RX_CH7_DMA_ACCESS_FAIL_INT_ST	The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT.

Links

() ()